(1) Field of the Invention
This invention relates to a method of making and the resultant structure for a high density self-aligned DRAM (Dynamic Random Access Memory) cell, and more particularly to a method for producing a stacked capacitor structure, as part of the DRAM cell, in a trench.
(2) Description of the Related Art
A typical DRAM cell consists of a single transistor and a storage capacitor. Digital information is stored in the capacitor and accessed through the transistor, by way of addressing the desired memory cell, which is connected with other such cells through an array of bit lines and word lines. In order to construct high density DRAMs in a reasonably sized chip area, both the transistor and capacitor elements must occupy less lateral space in each memory cell. As DRAMs are scaled down in dimensions, there is a continuous challenge to maintain a sufficiently high stored charge per capacitor unit area. Efforts to increase capacitance without increasing the planar area of the capacitor have been concentrated on building three dimensional capacitor structures, which increase the capacitor surface area. Thus cell structures have to change from the conventional planar-type capacitors to either trench capacitors or stack capacitors, in particular at densities above 4 Mbit.
When the stacked capacitor approach is used to fabricate 16 Mbit DRAMs and beyond, very complicated stacked structures are needed, such as fin structures, crown structures, and so forth. These typically are difficult to manufacture, and make it more difficult to form subsequent layers due to topological problems.
The trench capacitor is typically built in an opening in the substrate and thus does not affect the topology. When fabricating trench capacitors for DRAMs with densities of 16 Mbit and beyond, however, the trench needs to be very deep. There are technology and even theoretical physical limitations to processing the deep trenches that would be needed. As can be seen in "A 0.6 um2 256 Mb Trench DRAM Cell with Self-Aligned BuriED STrap (BEST)", by L. Nesbit et al, pp. 627-630, Tech. Dig. of IEDM, 1993, formation of a trench and the contact between the device and storage node is complex, very specific to trench formation and not applicable generally to forming a CMOS (Complementary Metal Oxide Semiconductor) technology module. Also, as can be seen in FIG. 5 of the above paper, the aspect ratio of the trench can be as large as 15-20, and the filling in of such a high aspect ratio well is extremely difficult. Other prior art single trenches are 10 to 15 micrometers deep with a diameter of 0.5 micrometers. A further problem with deep trenches is that the wafer may become mechanically unstable with so many deep trenches, for in a 64 Mbit memory, for example, 64 million trenches (at one capacitor per cell) are needed.
Workers in the art are aware of these problems, and have attempted to resolve them. For example, in U.S. Pat. No. 5,204,280 (Dhong et al) a method is shown for forming multiple pillars in a shallow trench in a silicon substrate. Hemispherical grain polysilicon is used as an etch mask to form the pillars. However, it is not shown how a node contact to a DRAM transistor would be formed, and the use of multiple pillars per trench increases the chip surface area occupied by the capacitor.